The present invention relates in general to integrated circuits and in particular to input/output (I/O) architecture and read/write system for high bandwidth semiconductor memories.
Increasing speed of operation and bandwidth have been major driving forces behind evolutionary changes in the design and development of memory circuits. In the case of dynamic random access memories (DRAMs), for example, the extended data output (EDO) architecture was developed to enhance memory bandwidth. With the introduction of the synchronous DRAM (SDRAM), the ability to pipeline the data as well as data pre-fetch schemes have helped increase the speed, throughput and bandwidth of the memory. This increase in bandwidth has not in all cases been without a tradeoff. The double data rate, or DDR SDRAM, for example, takes advantage of a two-bit pre-fetch technique to double the bandwidth of the memory circuit. This has been extended to quad data rate and above.
One drawback of these types of multiple data rate SDRAMs has been the corresponding increase in the number of I/O interconnect lines required to process the multiple bits during read and write operations. For example, in a DDR SDRAM having a by N (or xN, e.g., x16 or x32) organization, a 2-bit pre-fetch results in 2N bits of data being output from the memory array in read mode. Typically the total columns in an array are divided into two sets of even and odd columns, each delivering N bits of data. The 2N columns connect to a corresponding 2N sense amplifiers, with the 2N sense amplifiers driving 2N global I/O lines. A 2:1 parallel to serial conversion at the output takes place before the data is applied to the N data output (DQ) registers. The process is reversed for the write mode of operation wherein a serial-to-parallel conversion turns a serial bit stream into pairs of bits for DDR (quad bits for QDR, etc.).
Accordingly, a DDR SDRAM that has, for example, a x32organization and uses a complementary global I/O bus architecture (i.e., pair of lines per bit), requires 128 global I/O interconnect lines. Given an exemplary 2 micron pitch for each interconnect line, the 128 lines take up about 256 .mu.m which may be as much as 5% of the die size. This large number of global I/O lines therefore appreciably increases the overall size and cost of the memory device.